1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly but not exclusively to integrated circuit fabrication processes and structures.
2. Description of the Background Art
A metal oxide semiconductor field effect transistor (MOSFET) includes a source, a drain, and a gate. The source and the drain are typically formed in a substrate and separated by a channel. In an enhancement-type MOSFET, a channel sufficient to allow current flow between the source and the drain is not formed until the voltage on the gate relative to the source (vgs) equals or exceeds the threshold voltage (VT) of the MOSFET. Using complementary metal oxide semiconductor technology (CMOS), two kinds of enhancement-type MOSFETs may be fabricated in the same substrate. The first kind has a P-type channel and is referred to as a “PMOS transistor”, while the second kind has an N-type channel and is referred to as an “NMOS transistor.” PMOS and NMOS transistors may be separated by a shallow trench isolation (STI) structure.
FIG. 1 shows a schematic diagram of an example integrated circuit 100 in the middle of its fabrication process. FIG. 1 shows a PMOS transistor being formed in an N-well 105 and an NMOS transistor being formed in a P-well 106 after a gate oxidation step. The gate oxidation step formed gate oxides 108 and 109 for the PMOS and NMOS transistors, respectively. An STI structure 102 filled with field oxide (also referred to as “FILOX”) separates the PMOS and NMOS transistors. The region of the STI structure 102 overlying P-well 106 has been implanted with a P-type dopant during the formation of P-well 106, while the region of STI structure 102 overlying N-well 105 has been implanted with an N-type dopant during the formation of N-well 105. In FIG. 1, a dotted line 112 marks the division between the P-doped and N-doped regions of STI structure 102. An arrow 103 points towards the N-doped region and an arrow 104 points towards the P-doped region.
A problem with integrated circuit 100 is the difference in step height between the P-doped and N-doped regions of STI structure 102. This step height difference also referred to as “step height delta,” is generally bounded by dashed area 107. The step height difference may limit the operational window for a chemical mechanical polishing (CMP) step performed during the fabrication of STI structure 102. The operational window may specify a lower and an upper limit for the step height of the field oxide. In FIG. 1, dimension D110 illustrates a distance between the top and bottom exposed portions of the field oxide, while dimension D111 illustrates a distance between the top of the region where a gate is to be formed (i.e., “gate region”) and the bottom exposed portion of the field oxide. The limits for dimensions D110 and D111 may be dictated by the process window of the CMP step. For example, an excessive step height delta may limit the operational window for a silicon nitride CMP step and a silicon nitride strip step. Performing the silicon nitride CMP and silicon nitride strip steps on the upper side of the operational window may result in polystringer defects, while performing the steps on the lower side of the operational window may result in device stand-by current leakage. FIG. 2 shows a scanning electron micrograph (SEM) of an STI structure having an excessive step height delta (see dashed area 202) similar to that shown in FIG. 1.